Semiconductor device package and method of manufacturing the same

ABSTRACT

A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

BACKGROUND 1. Technical Field

The present disclosure relates to a semiconductor device package and amethod of manufacturing the same, and more particularly to asemiconductor device package with good shielding and heat dissipationcapabilities and a method of manufacturing the same.

2. Description of the Related Art

A semiconductor device package may include an electronic deviceoperating at a particular frequency, such as a radio frequencyintegrated circuit (RFIC), which may generate electromagneticinterference (EMI). The EMI can become particularly problematic when alayout density of components of the semiconductor device packageincreases and when the semiconductor device package becomesminiaturized. In addition, heat dissipation of a semiconductor devicepackage is another issue of concern.

SUMMARY

In some embodiments, according to one aspect, a semiconductor devicepackage includes a first circuit layer having a first surface and asecond surface opposite the first surface, a first electronic component,a shielding element, a shielding layer and a molding layer. The firstelectronic component is disposed over the first surface of the firstcircuit layer, and is electrically connected to the first circuit layer.The shielding element is disposed over the first surface of the firstcircuit layer, and is electrically connected to the first circuit layer.The shielding element is disposed adjacent to at least one side of thefirst electronic component. The shielding layer is disposed over thefirst electronic component and the shielding element, and the shieldinglayer is electrically connected to the shielding element. The moldinglayer encapsulates the first electronic component, the shielding elementand a portion of the shielding layer. An upper surface of the moldinglayer and an upper surface of the shielding layer are substantiallycoplanar.

In some embodiments, according to another aspect, a semiconductor devicepackage includes a circuit layer having a first surface and a secondsurface opposite the first surface, a first electronic component, asecond electronic component, a shielding element, a molding layer and ashielding layer. The first electronic component is disposed over thefirst surface of the circuit layer. The first electronic componentincludes a plurality of first conductive pillars extending toward thefirst surface and electrically connected to the circuit layer. Thesecond electronic component is disposed over the first surface of thecircuit layer and the first electronic component. The second electroniccomponent includes a plurality of second conductive pillars extendingtoward the first surface and electrically connected to the circuitlayer, the second electronic component partially overlapping the firstelectronic component, a length of at least one of the second conductivepillars being larger than a length of at least one of the firstconductive pillars. The shielding element is disposed over the firstsurface and is electrically connected to the circuit layer, and theshielding element is disposed adjacent to at least one side of the firstelectronic component and to at least one side of the second electroniccomponent. The molding layer encapsulates the first electroniccomponent, the second electronic component and the shielding element.The shielding layer is disposed over the molding layer and iselectrically connected to the shielding element. The carrier is disposedover the shielding layer.

In some embodiments, according to another aspect, a method ofmanufacturing a semiconductor device package includes forming ashielding layer over a carrier; forming a shielding element over theshielding layer; disposing a first electronic component over theshielding layer; disposing a molding layer to encapsulate the shieldinglayer, the shielding element and the first electronic component; andforming a first circuit layer over the molding layer, the shieldingelement and the first electronic component.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of some embodiments of the present disclosure are bestunderstood from the following detailed description when read with theaccompanying figures. It is noted that various structures may not bedrawn to scale, and dimensions of the various structures may bearbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a cross-sectional view of a semiconductor device package inaccordance with some embodiments of the present disclosure.

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F and FIG. 2Gillustrate an example of a manufacturing method of a semiconductordevice package in accordance with some embodiments of the presentdisclosure.

FIG. 3 is a cross-sectional view of a semiconductor device package inaccordance with some embodiments of the present disclosure.

FIG. 4 is a cross-sectional view of a semiconductor device package inaccordance with some embodiments of the present disclosure.

FIG. 5 is a cross-sectional view of a semiconductor device package inaccordance with some embodiments of the present disclosure.

FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, FIG. 6F, FIG. 6G and FIG.6H illustrate an example of a manufacturing method of a semiconductordevice package in accordance with some embodiments of the presentdisclosure.

FIG. 7 is a cross-sectional view of a semiconductor device package inaccordance with some embodiments of the present disclosure.

FIG. 8 is a cross-sectional view of a semiconductor device package inaccordance with some embodiments of the present disclosure.

FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, FIG. 9E and FIG. 9F illustrate anexample of a manufacturing method of a semiconductor device package inaccordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to explain certain aspects of the present disclosure. These are,of course, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters to refer to components of the variousexamples. This repetition is for the purpose of simplicity and clarityand does necessarily imply that components referred to by a samereference numeral and/or letter are identical. For example, some suchcomponents may be similar in some respects, but may differ in otherrespects.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,”“down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,”“lower,” “upper,” “over,” “under,” and so forth, are indicated withrespect to the orientation shown in the figures unless otherwisespecified. It should be understood that the spatial descriptions usedherein are for purposes of illustration only, and that practicalimplementations of the structures described herein can be spatiallyarranged in any orientation or manner, provided that the merits ofembodiments of this disclosure are not deviated from by sucharrangement.

The following description is directed to a semiconductor device package.In some embodiments, the semiconductor device package includes ashielding element disposed over a circuit layer and disposed adjacent toat least one side of an electronic component, and a shielding layerdisposed over the electronic component and electrically connected to theshielding element. The shielding layer and the shielding element areconfigured to function as an EMI shield and a heat sink for theelectronic component, and provide a ground path. The followingdescription is also directed to a method of manufacturing asemiconductor device package, as discussed below.

FIG. 1 is a cross-sectional view of a semiconductor device package 1 inaccordance with some embodiments of the present disclosure. As shown inFIG. 1, the semiconductor device package 1 includes a first circuitlayer 28, a first electronic component 20, a shielding element 16, ashielding layer 14 and a molding layer 24. The first circuit layer 28includes a first surface 281 facing the first electronic component 20,and a second surface 282 opposite to the first surface 281. In someembodiments, the first circuit layer 28 includes a redistribution layer(RDL) configured to reroute input/output paths corresponding toinput/output (I/O) contacts of the first electronic component 20. Insome embodiments, the first circuit layer 28 includes one or moreconductive wiring layers and one or more dielectric layers, which may bestacked adjacent to or on each other. In some embodiments, a conductivewiring layer proximal to the second surface 282 may function as or mayinclude bonding pads such as under bump metallurgies (UBMs).

The first electronic component 20 is disposed over a first surface 281of the first circuit layer 28, and is electrically connected to thefirst circuit layer 28. In some embodiments, the first electroniccomponent 20 includes a semiconductor die having an integrated circuit(IC) formed therein. In some embodiments, the first electronic component20 includes, but is not limited to, an active component such as anapplication specific IC (ASIC), a memory component such as a highbandwidth memory (HBM) component or another active component, and/or apassive component such as a capacitor, an inductor, a resistor or thelike. In some embodiments, conductive pillars 22 such as metal pillarsare disposed under a bottom surface 20B of the first electroniccomponent 20, and the first electronic component 20 is electricallyconnected to the first circuit layer 28 through the conductive pillars22. By way of example, the conductive pillars 22 include, but are notlimited to, copper pillars.

The shielding element 16 is disposed over the first surface 281 of thefirst circuit layer 28, and is electrically connected to the firstcircuit layer 28. The shielding element 16 is disposed adjacent to atleast one side 20S of the first electronic component 20. By way ofexample, the shielding element 16 may be disposed adjacent to one side20S, two sides 20S, three sides 20S or more sides 20S of the firstelectronic component 20. In some embodiments, the shielding element 16surrounds the sides 20S of the first electronic component 20 to shieldthe first electronic component 20 from EMI. In some embodiments, theshielding element 16 is configured to function as a part of a groundingpath. In some embodiments, the shielding element 16 is formed ofconductive material such as metal or metal alloy. By way of example, theconductive material may include, but is not limited to, copper, copperalloy, or the like.

The shielding layer 14 is disposed over the first electronic component20 and the shielding element 16. In some embodiments, the shieldinglayer 14 is formed of conductive material such as metal or alloy. By wayof example, the conductive material may include, but is not limited to,copper, copper alloy, or the like. In some embodiments, the shieldinglayer 14 is a conformal shielding, covering an upper surface 20U of thefirst electronic component 20 to provide an EMI shielding effect. Insome embodiments, the shielding layer 14 is configured to function asanother part of a grounding path. In some embodiments, the shieldinglayer 14 is electrically connected to the shielding element 16, formingan EMI shielding cap enclosing the upper surface 20U and the sides 20Sof the first electronic component 20. In some embodiments, the shieldinglayer 14 is in contact with the first electronic component 20, andconfigured to provide a heat dissipation path for the first electroniccomponent 20. In some embodiments, a width W (e.g. a horizontalextension, as shown in FIG. 1) of the shielding element 16 is largerthan a thickness T (e.g. a vertical extension, as shown in FIG. 1) ofthe shielding layer 14. The width W of the shielding element 16 and thethickness T of the shielding layer 14 may be modified as appropriatebased on desired shielding effect, heat dissipation effect or otherconsiderations.

The molding layer 24 encapsulates the first electronic component 20, theshielding element 16 and a portion of the shielding layer 14. In someembodiments, an upper surface 24U of the molding layer 24 and an uppersurface 14U of the shielding layer 14 are substantially coplanar. Insome embodiments, the material of the molding layer 24 includes, but isnot limited to, a molding compound such as an epoxy resin or the like,and fillers 24F such as silicon oxide fillers in the molding compound.In some embodiments, the fillers 24F disposed adjacent to the firstcircuit layer 28 have at least one cutting plane. In some embodiments, afirst interface S1 between the shielding layer 14 and the shieldingelement 16 and a second interface S2 between the shielding layer 14 andthe first electronic component 20 are substantially coplanar.

In some embodiments, the semiconductor device package 1 further includesfirst conductors 30 disposed over the second surface 282 of the firstcircuit layer 28, and electrically connected to the first circuit layer28. In some embodiments, the first conductors 30 include conductivebumps such as solder bumps, solder balls, solder pastes or the like. Insome embodiments, at least some of the first conductors 30 areelectrically connected to the first electronic component 20 through thefirst circuit layer 28, and are configured to provide an electricalconnection path to another electronic device such as a circuit board orthe like. In some embodiments, some other first conductors 30 areelectrically connected to the shielding element 16 through the firstcircuit layer 28, and are configured to connect to a grounding circuit.

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F and FIG. 2Gillustrate an example of a manufacturing method of the semiconductordevice package 1 in accordance with some embodiments of the presentdisclosure. As depicted in FIG. 2A, a shielding layer 14 is formed overa carrier 10. In some embodiments, a conductive film 12 configured tofunction as a seed layer is formed over the carrier 10 prior toformation of the shielding layer 14. In some embodiments, the conductivefilm 12 is a metal film such as a copper film or an alloy film such as atitanium/copper (Ti/Cu) film, which can be formed by pasting, sputteringor any other suitable technique. In some embodiments, the shieldinglayer 14 may, but need not, be formed by plating.

As shown in FIG. 2B, a shielding element 16 is formed over the shieldinglayer 14. In some embodiments, the shielding element 16 may, but neednot, be formed by plating. As shown in FIG. 2C, a first electroniccomponent 20 is bonded to the carrier 10 (e.g. via the shielding layer14 and/or the conductive film 12), and is disposed adjacent to theshielding element 16. In some embodiments, the first electroniccomponent 20 includes conductive pillars 22 such as conductive postsextending upward.

As shown in FIG. 2D, a molding layer 24 is disposed over the carrier 10to encapsulate the shielding layer 14, the shielding element 16 and thefirst electronic component 20. As shown in FIG. 2E, a portion of themolding layer 24 is removed to expose the shielding element 16. In someembodiments, the portion of the molding layer 24 is removed by grinding.In some embodiments, the conductive pillars 22 of the first electroniccomponent 20 are exposed after grinding.

As shown in FIG. 2F, a first circuit layer 28 is formed over the moldinglayer 24, the shielding element 16, the conductive pillars 22 and thefirst electronic component 20. In some embodiments, the first circuitlayer 28 is an RDL implemented by alternately forming several conductivewiring layers and several dielectric layers. The first circuit layer 28includes a first surface 281 facing the first electronic component 20,and a second surface 282 opposite to the first surface 281. In someembodiments, a conductive wiring layer proximal to the second surface282 may function as or may include bonding pads such as under bumpmetallurgies (UBMs). As shown in FIG. 2G, first conductors 30 are formedover the second surface 282 of the first circuit layer 28. The carrier10 and the conductive film 12 are removed from the shielding layer 14,and a singulation process is performed to form a semiconductor devicepackage 1 as illustrated in FIG. 1.

The semiconductor device package and manufacturing method of the presentdisclosure are not limited to the above-mentioned embodiments, and maybe implemented according to other embodiments. To streamline thedescription and for the convenience of comparison between variousembodiments of the present disclosure, similar components in each of thefollowing embodiments are marked with same numerals, and are notredundantly described.

FIG. 3 is a cross-sectional view of a semiconductor device package 2 inaccordance with some embodiments of the present disclosure. As shown inFIG. 3, different from the semiconductor device package 1, thesemiconductor device package 2 further includes a thermal conductiveelement 15 between the first electronic component 20 and the shieldinglayer 14. The thermal conductive element 15 is formed from a thermalconductive material, and is configured to function as a heat sink forenhancing heat dissipation of the first electronic component 20. In someembodiments, a first interface S1 between the shielding layer 14 and theshielding element 16 and a third interface S3 between the shieldinglayer 14 and the thermal conductive element 15 are substantiallycoplanar.

FIG. 4 is a cross-sectional view of a semiconductor device package 3 inaccordance with some embodiments of the present disclosure. As shown inFIG. 4, different from the semiconductor device package 1, thesemiconductor device package 3 further includes a second electroniccomponent 32 and a shielding compartment 34 (which may be, for example,a conductive post or pillar, such as a metallic conductive post orpillar). The second electronic component 32 is disposed over the firstsurface 281 of the first circuit layer 28, and is electrically connectedto the first circuit layer 28. In some embodiments, the secondelectronic component 32 is disposed adjacent to the first electroniccomponent 20. The shielding compartment 34 is disposed over the firstsurface 281 of the first circuit layer 28 and between the firstelectronic component 20 and the second electronic component 32. In someembodiments, the shielding compartment 34 is electrically connected tothe first circuit layer 28 and the shielding layer 14. The shieldingcompartment 34 is configured to block EMI transmission between the firstelectronic component 20 and the second electronic component 32. In someembodiments, the shielding layer 14 is in contact with the firstelectronic component 20 and the second electronic component 32. In somealternative embodiments, conductive elements 15 may be disposed betweenthe first electronic component 20 and the shielding layer 14, and/orbetween the second electronic component 32 and the shielding layer 14.

FIG. 5 is a cross-sectional view of a semiconductor device package 4 inaccordance with some embodiments of the present disclosure. As shown inFIG. 5, different from the semiconductor device package 3, thesemiconductor device package 4 further includes at least one conductivepost 36 and a second circuit layer 38. The at least one conductive post36 penetrates through the molding layer 24 and is electrically connectedto the first circuit layer 28. In some embodiments, the at least oneconductive post 36 is configured to electrically connect the firstcircuit layer 28 and the second circuit layer 38. In some embodiments,the at least one conductive post 36 may be, but is not limited to, ametal post such as a copper post. The second circuit layer 38 isdisposed over the molding layer 24, the shielding layer 14 and the atleast one conductive post 36, and is electrically connected to theshielding layer 14 and the at least one conductive post 36. The secondcircuit layer 38 includes a third surface 383 facing the first circuitlayer 28, and a fourth surface 384 opposite to the third surface 383. Insome embodiments, the second circuit layer 38 is a redistribution layer(RDL) configured to reroute input/output paths corresponding toinput/output (I/O) contacts of the first electronic component 20 and/orthe second electronic component 32. In some embodiments, the secondcircuit layer 38 includes one or more conductive wiring layers and oneor more dielectric layers stacked on each other. In some embodiments, aconductive wiring layer proximal to the fourth surface 384 may functionas or may include bonding pads such as under bump metallurgies (UBMs).

FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, FIG. 6F, FIG. 6G and FIG.6H illustrate an example of a manufacturing method of the semiconductordevice package 4 in accordance with some embodiments of the presentdisclosure. As depicted in FIG. 6A, a shielding layer 14 is formed overa carrier 10. In some embodiments, a conductive film 12 configured tofunction as a seed layer is formed over the carrier 10 prior toformation of the shielding layer 14. In some embodiments, the conductivefilm 12 is a metal film such as a copper film or an alloy film such as atitanium/copper (Ti/Cu) film, which can be formed by pasting, sputteringor any other suitable technique. In some embodiments, the shieldinglayer 14 may, but need not, be formed by plating.

As shown in FIG. 6B, a shielding element 16 is formed over the shieldinglayer 14. In some embodiments, the shielding element 16 may, but neednot, be formed by plating. At least one conductive post 36 is formedover the carrier 10 (e.g. over the conductive film 12). In someembodiments, the at least one conductive post 36 and the shieldingelement 16 are formed concurrently by the same process such as plating.In some embodiments, a shielding compartment 34 may be formed over theshielding layer 14 at this stage. As shown in FIG. 6C, a firstelectronic component 20 and a second electronic component 32 are bondedto the carrier 10 (e.g. via the conductive film 12 and the shieldinglayer 14). In some embodiments, the first electronic component 20 andthe second electronic component 32 include conductive pillars 22 such asconductive posts extending upward. In some embodiments, a thermalconductive element 15 is formed between at least one of: (i) the firstelectronic component 20 and the shielding layer 14, and (ii) the secondelectronic component 32 and the shielding layer 14.

As shown in FIG. 6D, a molding layer 24 is disposed over the carrier 10to encapsulate the shielding layer 14, the shielding element 16, theconductive post 36, the shielding compartment 34, the first electroniccomponent 20 and the second electronic component 32. As shown in FIG.6E, a portion of the molding layer 24 is removed to expose the shieldingelement 16, the shielding compartment 34 and the conductive post 36. Insome embodiments, the portion of the molding layer 24 is removed bygrinding. In some embodiments, the conductive pillars 22 of the firstelectronic component 20 and of the second electronic component 32 areexposed after grinding.

As shown in FIG. 6F, a first circuit layer 28 is formed over the moldinglayer 24, the shielding element 16, the conductive post 36, theshielding compartment 34, the first electronic component 20 and thesecond electronic component 32. In some embodiments, the first circuitlayer 28 is an RDL implemented by alternately forming several conductivewiring layers and several dielectric layers. The first circuit layer 28includes a first surface 281 facing the first electronic component 20,and a second surface 282 opposite to the first surface 281. In someembodiments, the conductive wiring layer proximal to the second surface282 may function as or may include bonding pads such as under bumpmetallurgies (UBMs). Then, first conductors 30 are formed over thesecond surface 282 of the first circuit layer 28.

As shown in FIG. 6G, the first conductors 30 are mounted on a supporter11, the semiconductor package may be flipped, and the carrier 10 and theconductive film 12 are removed from the shielding layer 14. In someembodiments, the supporter 11 is a tape attached to the second surfaceof the first circuit layer 28 and enclosing the first conductors 30. Insome embodiments, residual conductive film 12 is removed from theshielding layer 14, the molding layer 24 and the at least one conductivepost 36 by, for example, grinding or etching.

As shown in FIG. 6H, the second circuit layer 38 is formed over theshielding layer 14, the molding layer 24 and the at least one conductivepost 36. The second circuit layer 38 includes a third surface 383 facingthe first circuit layer 28, and a fourth surface 384 opposite to thethird surface 383. The supporter 11 is then removed from the firstconductors 30, and a singulation process is performed to form asemiconductor device package 4 as illustrated in FIG. 5.

FIG. 7 is a cross-sectional view of a semiconductor device package 5 inaccordance with some embodiments of the present disclosure. As shown inFIG. 7, different from the semiconductor device package 4, thesemiconductor device package 5 further includes an electronic device 50disposed over and electrically connected to the second circuit layer 38.In some embodiments, the electronic device 50 may, but need not, beanother semiconductor device package having similar structure as thesemiconductor device packages 3 or 4. In some embodiments, thesemiconductor device package 5 further includes second conductors 48disposed between and electrically connected to both the second circuitlayer 38 and the electronic device 50. In some embodiments, the secondconductors 48 include conductive bumps such as solder bumps, solderballs, solder pastes or the like. In some embodiments, at least some ofthe second conductors 48 are electrically connected to the firstelectronic component 20 and the second electronic component 32 throughthe second circuit layer 38, and are electrically connected to theelectronic device 50. In some embodiments, at least some of the secondconductors 48 and a portion of first conductors 30 are configured toconnect to a grounding circuit.

FIG. 8 is a cross-sectional view of a semiconductor device package 6 inaccordance with some embodiments of the present disclosure. As shown inFIG. 8, the semiconductor device package 6 includes a circuit layer 82,a first electronic component 70, a second electronic component 76, ashielding element 66, a molding layer 80, a shielding layer 62 and acarrier 60. The first electronic component 70 is disposed over a firstsurface 821 of the circuit layer 82. In some embodiments, the circuitlayer 82 is a redistribution layer (RDL) configured to rerouteinput/output paths corresponding to input/output (I/O) contacts of thefirst electronic component 70 and/or the second electronic component 76.The first electronic component 70 includes first conductive pillars 72extending toward the first surface 821 and electrically connected to thecircuit layer 82. The second electronic component 76 is disposed overthe first surface 821 of the circuit layer 82 and at least a portion ofthe first electronic component 70. The second electronic component 76includes second conductive pillars 78 extending toward the first surface821 and electrically connected to the circuit layer 82. The secondelectronic component 76 partially overlaps the first electroniccomponent 70 (e.g. a portion of the second electronic component 76 isdisposed over the first electronic component 70, and another portion ofthe second electronic component 76 is not disposed over the firstelectronic component 70), and a length L2 of at least one of the secondconductive pillars 78 is larger than a length L1 of at least one of thefirst conductive pillars 72. In some embodiments, the first electroniccomponent 70 and the second electronic component 76 are semiconductordies having an integrated circuit formed therein. In some embodiments,each of the first electronic component 70 and the second electroniccomponent 76 may, but need not, include any of an active component suchas an application specific IC (ASIC), a memory component such as a highbandwidth memory (HBM) component or another active component, and/or apassive component such as a capacitor, an inductor, a resistor or thelike.

The shielding element 66 is disposed over the first surface 821 and iselectrically connected to the circuit layer 82. The shielding element 66is adjacent to at least one side of the first electronic component 70and the second electronic component 76. By way of example, the shieldingelement 66 may be disposed adjacent one side, two sides, three sides ormore sides of the first electronic component 70 and the secondelectronic component 76. In some embodiments, the shielding element 66surrounds the sides of the first electronic component 70 and the secondelectronic component 76 and helps to reduce EMI. In some embodiments,the shielding element 66 is configured to function as a part of agrounding path. In some embodiments, the shielding element 66 is formedof conductive material such as metal or alloy. By way of example, theconductive material may include, but is not limited to, copper, copperalloy, or the like.

The molding layer 80 encapsulates the first electronic component 70, thesecond electronic component 76 and the shielding element 66. Theshielding layer 62 is disposed over the molding layer 80 and iselectrically connected to the shielding element 66. In some embodiments,the material of the molding layer 80 includes, but is not limited to, amolding compound such as an epoxy resin or the like, and fillers such assilicon oxide fillers in the molding compound. The carrier 60 isdisposed over the shielding layer 62. In some embodiments, the carrier60 is a semiconductor carrier such as a silicon carrier. In someembodiments, the carrier 60 is configured to enhance robustness and heatdissipation for the semiconductor device package 6.

In some embodiments, the semiconductor device package 6 further includesan insulating layer 64 disposed between the molding layer 80 and theshielding layer 62. The insulating layer 64 defines an opening 64H, andthe shielding layer 62 and the shielding element 66 are electricallyconnected through the opening 64H of the insulating layer 64.

In some embodiments, the semiconductor device package 6 further includesconductors 86 disposed over a second surface 822 of the circuit layer 82and electrically connected to the circuit layer 82. In some embodiments,the conductors 86 include conductive bumps such as solder bumps, solderballs, solder pastes or the like. In some embodiments, at least some ofthe conductors 86 are electrically connected to the first electroniccomponent 70 and/or the second electronic component 76 through thecircuit layer 82, and are configured to create an electrical connectionpath to another electronic device such as a circuit board or the like.In some embodiments, some other conductors 86 are electrically connectedto the shielding element 66 through the circuit layer 82, and areconfigured to connect to a grounding circuit.

FIG. 9A, FIG. 9B, FIG. 9C, FIG. 9D, FIG. 9E and FIG. 9F illustrate anexample of a manufacturing method of the semiconductor device package 6in accordance with some embodiments of the present disclosure. Asdepicted in FIG. 9A, a shielding layer 62 is formed over a carrier 60.In some embodiments, an insulating layer 64 is formed over the shieldinglayer 62. The insulating layer 64 defines one or more openings 64Hexposing the shielding layer 62.

As shown in FIG. 9B, a shielding element 66 is formed over the shieldinglayer 64. In some embodiments, the shielding element 66 is electricallyconnected to the shielding layer 64 through the opening 64H of theinsulating layer 64. As shown in FIG. 9C, a second electronic component76 is bonded to the carrier 60 (e.g. via the insulating layer 64 and theshielding layer 62), adjacent to the shielding element 16. In someembodiments, the second electronic component 76 includes conductivepillars 78 such as conductive posts extending upward.

As shown in FIG. 9D, a first electronic component 70 is formed over atleast a portion of the second electronic component 76. The firstelectronic component 70 includes a plurality of second conductivepillars 72 extending upward. The second electronic component 76partially overlaps the first electronic component 70, and a length L2 ofat least one of the second conductive pillars 78 is larger than a lengthL1 of at least one of the first conductive pillars 72.

As shown in FIG. 9E, a molding layer 80 is disposed over the carrier 10to encapsulate the shielding layer 64, the shielding element 66, thefirst electronic component 72 and the second electronic component 76. Aportion of the molding layer 80 is removed to expose the shieldingelement 66. In some embodiments, the portion of the molding layer 80 isremoved by grinding. In some embodiments, the conductive pillars 72 ofthe first electronic component 70 and the conductive pillars 78 of thesecond electronic component 76 are exposed after grinding.

As shown in FIG. 9F, a circuit layer 82 is formed over the molding layer80, the shielding element 66, the first electronic component 70 and thesecond electronic component 76. In some embodiments, the circuit layer82 is an RDL implemented by alternately forming several conductivewiring layers and several dielectric layers. The circuit layer 82includes a first surface 821 facing the first electronic component 70and the second electronic component 76, and a second surface 822opposite to the first surface 821. In some embodiments, the conductivewiring layer proximal to the second surface 822 may function as or mayinclude bonding pads such as under bump metallurgies (UBMs). Conductors86 are formed over the second surface 822 of the circuit layer 82 toform a semiconductor device package 6 as illustrated in FIG. 8.

A semiconductor device package of various embodiments of the presentdisclosure is compatible with wafer level chip scale packaging (WLCSP).The semiconductor device package is compatible with package on packagestructure, and 2.5D/3D packaging. The shielding layer and the shieldingelement can form a conformal EMI shielding for the electroniccomponent(s), and the conformal EMI shielding makes it possible tofurther reduce the size of the semiconductor device package. Theshielding layer may also be configured to function as a heat sink forenhancing heat dissipation for the electronic component(s). Theelectronic components can partially overlap, and can be electricallyconnected to a circuit layer. Thus, the size of the semiconductor devicepackage is reduced, and electrical communication is implemented in ashorter path, which increases bandwidth and speed and reduces powerconsumption.

As used herein, the singular terms “a,” “an,” and “the” may includeplural referents unless the context clearly dictates otherwise.

As used herein, the terms “conductive,” “electrically conductive” and“electrical conductivity” refer to an ability to transport an electriccurrent. Electrically conductive materials typically indicate thosematerials that exhibit little or no opposition to the flow of anelectric current. One measure of electrical conductivity is Siemens permeter (S/m). Typically, an electrically conductive material is onehaving a conductivity greater than approximately 10⁴ S/m, such as atleast 10⁵ S/m or at least 10⁶ S/m. The electrical conductivity of amaterial can sometimes vary with temperature. Unless otherwisespecified, the electrical conductivity of a material is measured at roomtemperature.

As used herein, the terms “approximately,” “substantially,”“substantial” and “about” are used to describe and account for smallvariations. When used in conjunction with an event or circumstance, theterms can refer to instances in which the event or circumstance occursprecisely as well as instances in which the event or circumstance occursto a close approximation. For example, when used in conjunction with anumerical value, the terms can refer to a range of variation of lessthan or equal to ±10% of that numerical value, such as less than orequal to ±5%, less than or equal to ±4%, less than or equal to ±3%, lessthan or equal to ±2%, less than or equal to ±1%, less than or equal to±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. Forexample, two numerical values can be deemed to be “substantially” thesame or equal if a difference between the values is less than or equalto ±10% of an average of the values, such as less than or equal to ±5%,less than or equal to ±4%, less than or equal to ±3%, less than or equalto ±2%, less than or equal to ±1%, less than or equal to ±0.5%, lessthan or equal to ±0.1%, or less than or equal to ±0.05%. For example,“substantially” parallel can refer to a range of angular variationrelative to 0° that is less than or equal to ±10°, such as less than orequal to ±5°, less than or equal to ±4° , less than or equal to ±3°,less than or equal to ±2°, less than or equal to ±1°, less than or equalto ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.For example, “substantially” perpendicular can refer to a range ofangular variation relative to 90° that is less than or equal to ±10°,such as less than or equal to ±5°, less than or equal to ±4°, less thanor equal to ±3°, less than or equal to ±2°, less than or equal to ±1°,less than or equal to ±0.5°, less than or equal to ±0.1°, or less thanor equal to ±0.05°.

Two surfaces can be deemed to be coplanar or substantially coplanar if adisplacement between the two surfaces is no greater than 5 μm, nogreater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.

Additionally, amounts, ratios, and other numerical values are sometimespresented herein in a range format. It is to be understood that suchrange format is used for convenience and brevity and should beunderstood flexibly to include numerical values explicitly specified aslimits of a range, but also to include all individual numerical valuesor sub-ranges encompassed within that range as if each numerical valueand sub-range is explicitly specified.

While the present disclosure has been described and illustrated withreference to specific embodiments thereof, these descriptions andillustrations do not limit the present disclosure. It should beunderstood by those skilled in the art that various changes may be madeand equivalents may be substituted without departing from the truespirit and scope of the present disclosure as defined by the appendedclaims. The illustrations may not be necessarily drawn to scale. Theremay be distinctions between the artistic renditions in the presentdisclosure and the actual apparatus due to manufacturing processes andtolerances. There may be other embodiments of the present disclosurewhich are not specifically illustrated. The specification and drawingsare to be regarded as illustrative rather than restrictive.Modifications may be made to adapt a particular situation, material,composition of matter, method, or process to the objective, spirit andscope of the present disclosure. All such modifications are intended tobe within the scope of the claims appended hereto. While the methodsdisclosed herein have been described with reference to particularoperations performed in a particular order, it will be understood thatthese operations may be combined, sub-divided, or re-ordered to form anequivalent method without departing from the teachings of the presentdisclosure. Accordingly, unless specifically indicated herein, the orderand grouping of the operations are not limitations of the presentdisclosure.

1. A semiconductor device package, comprising: a first circuit layerhaving a first surface and a second surface opposite to the firstsurface; a first electronic component disposed over the first surface ofthe first circuit layer, and electrically connected to the first circuitlayer; a shielding element disposed over the first surface of the firstcircuit layer, and electrically connected to the first circuit layer,wherein the shielding element is disposed adjacent to at least one sideof the first electronic component; a shielding layer disposed over thefirst electronic component and over the shielding element, wherein theshielding layer is electrically connected to the shielding element;[[and]] a molding layer encapsulating the first electronic component,the shielding element and a portion of the shielding layer, wherein anupper surface of the molding layer and an upper surface of the shieldinglayer are substantially coplanar; at least one conductive post extendingthrough the molding layer and electrically connected to the firstcircuit layer; a second circuit layer disposed over the molding layer,the shielding layer and the at least one conductive post, andelectrically connected to the shielding layer and to the at least oneconductive post and an electronic device disposed over and electricallyconnected to the second circuit layer.
 2. The semiconductor devicepackage of claim 1, wherein the shielding layer is in contact with thefirst electronic component.
 3. The semiconductor device package of claim2, wherein a first interface between the shielding layer and theshielding element and a second interface between the shielding layer andthe first electronic component are substantially coplanar.
 4. Thesemiconductor device package of claim 1, further comprising a thermalconductive element disposed between the first electronic component andthe shielding layer.
 5. The semiconductor device package of claim 4,wherein a first interface between the shielding layer and the shieldingelement and a second interface between the shielding layer and thethermal conductive element are substantially coplanar.
 6. Thesemiconductor device package of claim 1, wherein the molding layercomprises a plurality of fillers, and at least some fillers adjacent tothe first circuit layer have at least one cutting plane.
 7. Thesemiconductor device package of claim 1, wherein a width of theshielding element is larger than a thickness of the shielding layer. 8.The semiconductor device package of claim 1, further comprising aplurality of first conductors disposed over the second surface of thefirst circuit layer, and electrically connected to the first circuitlayer.
 9. The semiconductor device package of claim 1, wherein theshielding element surrounds all sides of the first electronic component.10. The semiconductor device package of claim 1, further comprising: asecond electronic component disposed over the first surface of the firstcircuit layer, and electrically connected to the first circuit layer;and a shielding compartment disposed over the first surface of the firstcircuit layer and disposed between the first electronic component andthe second electronic component, wherein the shielding compartment iselectrically connected to the first circuit layer and the shieldinglayer.
 11. (canceled)
 12. The semiconductor device package of claim 1,further comprising a plurality of second conductors disposed between andelectrically connected to the second circuit layer and the electronicdevice. 13.-20. (canceled)
 21. A semiconductor device package,comprising: a circuit layer having a first surface and a second surfaceopposite to the first surface; a first electronic component disposedover the first surface of the circuit layer, and electrically connectedto the circuit layer; a shielding element disposed over the firstsurface of the circuit layer, and electrically connected to the circuitlayer; a shielding layer disposed over the first electronic componentand over the shielding element, wherein the shielding layer iselectrically connected to the shielding element; a molding layerencapsulating the first electronic component and the shielding element,wherein an upper surface of the molding layer and an upper surface ofthe shielding layer are substantially coplanar; a second electroniccomponent disposed over the first surface of the circuit layer, andelectrically connected to the circuit layer; and a shielding compartmentdisposed over the first surface of the circuit layer and disposedbetween the first electronic component and the second electroniccomponent, wherein the shielding compartment is electrically connectedto the circuit layer and the shielding layer.
 22. The semiconductordevice package of claim 21, wherein the shielding layer is in contactwith the first electronic component.
 23. The semiconductor devicepackage of claim 22, wherein a first interface between the shieldinglayer and the shielding element and a second interface between theshielding layer and the first electronic component are substantiallycoplanar.
 24. The semiconductor device package of claim 21, furthercomprising a thermal conductive element disposed between the firstelectronic component and the shielding layer.
 25. The semiconductordevice package of claim 24, wherein a first interface between theshielding layer and the shielding element and a second interface betweenthe shielding layer and the thermal conductive element are substantiallycoplanar.
 26. (canceled)
 27. A semiconductor device package, comprising:a circuit layer having a first surface and a second surface opposite tothe first surface; an electronic component disposed over the firstsurface of the circuit layer, and electrically connected to the circuitlayer; a shielding layer disposed over the electronic component; and amolding layer encapsulating the electronic component, wherein themolding layer comprises a plurality of fillers, and at least somefillers adjacent to the circuit layer respectively have one or morecutting planes, the one or more cutting planes disposed along the firstsurface of the circuit layer.
 28. The semiconductor device package ofclaim 27, further comprising a shielding element disposed over the firstsurface of the circuit layer, and electrically connected to the circuitlayer.
 29. The semiconductor device package of claim 27, wherein theelectronic component has a bottom surface facing the first surface ofthe circuit layer, and the one or more cutting planes are substantiallyparallel to the bottom surface of the electronic component.
 30. Asemiconductor device package, comprising: a first circuit layer having afirst surface and a second surface opposite to the first surface; afirst electronic component disposed over the first surface of the firstcircuit layer, and electrically connected to the first circuit layer; ashielding element disposed over the first surface of the first circuitlayer, and electrically connected to the first circuit layer, whereinthe shielding element surrounds four sides of the first electroniccomponent; a shielding layer disposed over the first electroniccomponent and over the shielding element, wherein the shielding layer iselectrically connected to the shielding element; and a molding layerencapsulating the first electronic component, the shielding element anda portion of the shielding layer, and disposed between the firstelectronic component and the first surface of the first circuit layer,wherein an upper surface of the molding layer and an upper surface ofthe shielding layer are substantially coplanar.
 31. The semiconductordevice package of claim 30, wherein a bottom surface of the shieldinglayer, an upper surface of the first electronic component and an uppersurface of the shielding element are substantially coplanar.